A switched mode power supply output stage is known from IR Design Tips, “High Current Buffer For Control IC's,” DT-92-2A, which shows a CMOS buffer circuit which can be used as an output power stage of a control integrated circuit or a power stage in a gate driver circuit. The output stage consists of one p-channel and one n-channel transistor (Q3 and Q4) in a CMOS inverter connection. The turn-off of the output p-channel transistor (Q3) is assisted by another p-channel transistor (Q1) in a common source connection which speeds-up the discharging of the gate of the power switch (Q3). In a similar manner, a n-channel transistor (Q2) speeds-up the discharging of the gate of the output n-channel switch (Q4).
When the gate input signal is low, the speed-up transistor (Q1) is turned-on, securing a fast discharging of the gate of the p-channel MOS transistor switch (Q3) and a slower charging of the n-channel MOS transistor (Q4). The delay in turning-on the n-channel transistor switch (Q4) is determined by the RC constant formed by the resistor R1 and the input capacitance of the transistor (Q4). This delay is utilized to minimize the time period when both switches are on to minimize the cross-current flowing through the output inverter (Q3 and Q4).
In a similar way, when the input signal is going high, the speed-up transistor (Q2) secures a fast turn-off of the n-channel transistor switch (Q4) and a delayed turn-on of the p-channel transistor switch (Q3). This circuit enables the use of a CMOS inverter topology to provide several watts of output power, a power range where a cross-current associated with a simultaneous switching of the inverter transistors would lead to a prohibitively high power dissipation.
Utilization of speed-up transistors for allowing a hard turn-off of the power MOSFET and so minimizing the power losses related to switching events, would advantageously utilize monolithic integration of the speed-up transistors and the power switch transistors. Monolithic integration is the most effective way to minimize the parasitic inductance in the connections between the speed-up transistor and the main power switch, making the hard turn-off more effective. Vertical power MOSFET devices are usually designed with the drain electrode placed at the back-side of the die. Thus, the utilization of a technology for vertical MOSFETs, the back-side of the die acting as the source terminal would enable such monolithic integration. These devices would provide a minimum internal capacitance, and especially a minimum gate-to-drain capacitance (Cgd) which dictates the speed of the voltage transient across the transistor during switching events. The steeper the wave forms, the lower the power loss during switching.